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fo technology

technology overview

we offer both chip first and chip last solutions. for chip first technology,first step is place die face down on the temporary carrier with adhesion layer. the second step is to cover the die surface by molding compound (emc). the third step is to remove the adhesion layer and the temporary carrier through thermal release; finally, rdl layer and solder ball are directly made on die& compound surface.

fan out can use not only compound materials, but also substrates, thus expanding the fan out package to another type: fan out package on substrate (fopos).

applications

we will optimize our solutions to meet customer requirements. fo technologies are used in mic, rf, cpu, gpu and network.

features

　◆ fo size: 32x26mm

　◆ advance nodes to 16 nm

　◆ rdl l/s: 2/2um

　◆ rdl layer: 3 layers

package types

　◆ ewlb

　◆ fopos-chip first face down

　◆ fopos-chip first face up

　◆ fopos-chip last

key advantages include

　◆ low cost than 2.5d

　◆ good electrical performance

　◆ high i/o pin counts

we also offer extensive test developments for products and are experienced in cpu, apu, gpu, chipset, digital audio, baseband, microcontroller, lcd driver, touch panel driver.